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? semiconductor components industries, llc, 2014 october, 2014 ? rev. 9 1 publication order number: mc74hc165a/d mc74hc165a 8-bit serial or parallel-input/ serial-output shift register high?performance silicon?gate cmos the mc74hc165a is identical in pinout to the ls165. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this device is an 8?bit shift register with complementary outputs from the last stage. data may be loaded into the register either in parallel or in serial form. when the serial shift/parallel load input is low, the data is loaded asynchronously in parallel. when the serial shift/parallel load input is high, the data is loaded serially on the rising edge of either clock or clock inhibit (see the function table). the 2?input nor clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7 a ? chip complexity: 286 fets or 71.5 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free and are rohs compliant see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information marking diagrams soic?16 d suffix case 751b tssop?16 dt suffix case 948f 1 1 6 pdip?16 n suffix case 648 1 16 1 16 1 16 mc74hc165an awlyywwg 1 16 hc165ag awlyww hc 165a alyw 1 16 a = assembly lo- cation l, wl = wafer lot y, yy = year w, ww = work week g or = pb?free package (note: microdot may be in either location) 165a alyw qfn16 mn suffix case 485aw 1 www. onsemi.com
mc74hc165a www. onsemi.com 2 pin 16 = v cc pin 8 = gnd 11 12 13 14 3 4 5 6 10 a b c d e f g h s a parallel data inputs serial data input serial shift/ parallel load 1 2 15 clock clock inhibit 9 7 q h q h serial data outputs figure 1. pin assignments 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 b c d clock inhibit v cc q h s a a f e clock serial shift/ parallel load gnd q h h g figure 2. logic diagram 116 215 314 413 512 611 710 89 gnd b c d clock inhibit v cc q h s a a f e clock serial shift/ parallel load gnd q h h g function table inputs internal stages output operation serial shift/ parallel load clock clock inhibit s a a ? h q a q b q h l x x x a h a b h asynchronous parallel load h h l l l h x x l h q an q an q gn q gn serial shift via clock h h l l l h x x l h q an q an q gn q gn serial shift via clock inhibit h h x h h x x x x x no change inhibited clock h l l x x no change no clock x = don?t care q an ? q gn = data shifted from the preceding stage
mc74hc165a www. onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ? 0.5 to + 7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air plastic dip? soic package? tssop package? 750 500 450 mw t stg storage temperature ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip, soic or tssop package) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ?derating ? plastic dip: ? 10 mw/ c from 65 to 125 c soic package: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 + 125 c t r , t f input rise and fall time v cc = 2.0 v (figure 1) v cc = 3.0 v v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 600 500 400 ns functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recommended operating ranges limits may affect device reliability. dc electrical characteristics (voltages referenced to gnd) symbo l parameter test conditions v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c v ih minimum high?level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 v v il maximum low?level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 v v oh minimum high?level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | 2.4 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc165a www. onsemi.com 4 dc electrical characteristics (voltages referenced to gnd) symbol unit guaranteed limit v cc v test conditions parameter symbol unit 125 c 85 c ? 55 to 25 c v cc v test conditions parameter v ol maximum low?level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. ac electrical characteristics (c l = 50 pf, input t r = t f = 6 ns) symbo l parameter v cc v guaranteed limit unit ? 55 to 25 c 85 c 125 c f max maximum clock frequency (50% duty cycle) (figures 1 and 8) 2.0 3.0 4.5 6.0 6 18 30 35 4.8 17 24 28 4 15 20 24 mhz t plh , t phl maximum propagation delay, clock (or clock inhibit) to q h or q h (figures 1 and 8) 2.0 3.0 4.5 6.0 150 52 30 26 190 63 38 33 225 65 45 38 ns t plh , t phl maximum propagation delay, serial shift/parallel load to q h or q h (figures 2 and 8) 2.0 3.0 4.5 6.0 175 58 35 30 220 70 44 37 265 72 53 45 ns t plh , t phl maximum propagation delay, input h to q h or q h (figures 3 and 8) 2.0 3.0 4.5 6.0 150 52 30 26 190 63 38 33 225 65 45 38 ns t tlh , t thl maximum output transition time, any output (figures 1 and 8) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns c in maximum input capacitance ? 10 10 10 pf c pd power dissipation capacitance (per package)* typical @ 25 c, v cc = 5.0 v pf 40 * used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc165a www. onsemi.com 5 timing requirements (input t r = t f = 6 ns) ???? ???? ???? symbo l ????????????????? ????????????????? ????????????????? ??? ??? ??? ?????????? ?????????? ??? ??? ??? ????? ????? c ???? ???? 85 c ??? ??? 125 c ???? ???? ???? t su ????????????????? ????????????????? ????????????????? ??? ??? ??? ????? ????? ????? ???? ???? ???? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ????????????????? ????????????????? ????????????????? ??? ??? ??? ????? ????? ????? ???? ???? ???? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ????????????????? ????????????????? ????????????????? ????????????????? ??? ??? ??? ??? ????? ????? ????? ????? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ???
mc74hc165a www. onsemi.com 6 pin descriptions inputs a, b, c, d, e, f, g, h (pins 11, 12, 13, 14, 3, 4, 5, 6) parallel data inputs. data on these inputs are asynchronously entered in parallel into the internal flip?flops when the serial shift/parallel load input is low. sa (pin 10) serial data input. when the serial shift/parallel load input is high, data on this pin is serially entered into the first stage of the shift register with the rising edge of the clock. control inputs serial shift/parallel load (pin 1) data?entry control input. when a high level is applied to this pin, data at the serial data input (sa) are shifted into the register with the rising edge of the clock. when a low level is applied to this pin, data at the parallel data inputs are asynchronously loaded into each of the eight internal stages. clock, clock inhibit (pins 2, 15) clock inputs. these two clock inputs function identically. either may be used as an active?high clock inhibit. however, to avoid double clocking, the inhibit input should go high only while the clock input is high. the shift register is completely static, allowing clock rates down to dc in a continuous or intermittent mode. outputs q h , q h (pins 9, 7) complementary shift register outputs. these pins are the noninverted and inverted outputs of the eighth stage of the shift register. ordering information device package shipping ? MC74HC165ANG pdip?16 (pb?free) 500 units / rail mc74hc165adg soic?16 (pb?free) 48 units / rail mc74hc165adr2g soic?16 (pb?free) 2500 units / reel nlv74hc165adr2g* soic?16 (pb?free) 2500 units / reel mc74hc165adtr2g tssop?16 (pb?free) 2500 units / reel nlv74hc165adtr2g* tssop?16 (pb?free) 2500 units / reel mc74hc165amntwg qfn16 (pb?free) 3000 units / reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc74hc165a www. onsemi.com 7 switching waveforms t r t f v cc gnd 90% 50% 10% t plh t phl clock or clock inhibit 90% 50% 10% t tlh t thl q h or q h serial shift/ parallel load q h or q h 50% t plh 50% v cc gnd t phl 50% t r t f input h 90% 50% 10% 90% 50% 10% v cc gnd t phl t thl t tlh t plh q h or q h 50% v cc gnd t h v cc gnd asynchronous parallel load (level sensitive) serial shift/ parallel load inputs a-h input s a 50% 50% clock or clock inhibit v cc gnd v cc gnd serial shift/ parallel load clock or clock inhibit 50% 50% t su v cc gnd v cc gnd clock 2 inhibited clock inhibit clock 50% 50% t su t rec v cc gnd v cc gnd *includes all probe and jig capacitance c l * test point device under test output t w 1/f max t w valid t su valid t su t h t h figure 3. serial?shirt mode figure 4. parallel?load mode figure 5. parallel?load mode figure 6. parallel?load mode figure 7. serial?shift mode figure 8. serial?shift mode figure 9. serial?shift, clock?inhibit mode figure 10. test circuit
mc74hc165a www. onsemi.com 8 abc fgh 11 12 13 4 5 6 9 q h 7 q h serial shift/ parallel load 1 serial data input s a 10 clock 2 clock inhibit 15 expanded logic diagram clock clock inhibit s a serial shift/ parallel load a b c d e f g h q h q h h l h l h l h h hh ll l h h l l h h l l h h l parallel load parallel data inputs timing diagram dq a cc dq b cc dq c cc dq f cc dq g cc dq h cc clock inhibit mode serial-shift mode
mc74hc165a www. onsemi.com 9 package dimensions pdip?16 case 648?08 issue u 18 16 9 b2 note 8 d a top view e1 b b l a1 a c seating plane 0.010 ca side view m 16x d1 e a2 note 3 m b m eb e end view end view with leads constrained dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.735 0.775 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 18.67 19.69 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs?3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension e3 is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ c a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81 h note 5 note 6 m e/2
mc74hc165a www. onsemi.com 10 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint 16 89 8x
mc74hc165a www. onsemi.com 11 package dimensions tssop?16 case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint
mc74hc165a www. onsemi.com 12 package dimensions qfn16, 2.5x3.5, 0.5p case 485aw issue o dim min max millimeters a a1 0.00 0.05 a3 b 0.20 0.30 d 2.50 bsc d2 0.85 1.15 e 3.50 bsc e2 e 0.50 bsc k 0.20 --- notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimensions b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 0.20 ref b d2 l pin one e2 1 8 15 10 d e b a c 0.15 c 0.15 2x 2x e 2 16x 16x 0.10 c 0.05 c a b note 3 a 16x k a1 (a3) seating plane c 0.08 c 0.10 0.80 1.00 l 0.35 0.45 1.85 2.15 l1 detail a l alternate terminal constructions l ??? *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.80 3.80 1.10 0.50 0.60 16x 0.30 16x dimensions: millimeters 1 reference top view side view note 4 c 0.15 c a b 0.15 c a b detail a bottom view e/2 l1 --- 0.15 2.10 pitch package outline p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc165ad literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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